The present invention relates to a method and flexible circuit interposer and, in particular, to a method and flexible circuit interposer having high-aspect ratio conductors therethrough.
As semiconductor integrated circuit technology has advanced to greatly increase the amount and operating speed of the circuitry that can be fabricated on a single semiconductor chip, it has become more difficult to effectively utilize such integrated circuits due to the greatly increased number of input and output connections to the chip and the decreasing spacing or pitch of those connections. The connection problem has become more severe where the number of connections exceeds that conveniently or economically attainable in a conventional mechanical package.
One approach to solve this problem utilizes semiconductor chips mounted with contacts against and connecting to corresponding contacts on the next-level circuit board, the so-called xe2x80x9cflip-chipxe2x80x9d mounting. This flip-chip technique requires that the contacts on the next-level circuit board be of substantially the same size and of the same pitch as are those on the semiconductor chip, however, the pitch of the semiconductor chip connections has become much finer than the pitch attainable on conventional substrates and printed wiring circuit boards to which such semiconductor chips are mounted. In addition, the differences in thermal expansion between the semiconductor chip and the next-level circuit board caused by differences in the coefficient of thermal expansion (CTE) of the materials produces thermally-induced stress that can lead to failure and/or degradation of the interconnections when exposed to temperature extremes, such as in thermal cycling or soldering.
A further solution to these problems has employed an intermediate substrate between the semiconductor chip and the next-level circuit board to absorb some of the thermally-induced stress, and also to allow the fanning out of the connections to the semiconductor chip to permit a larger contact size and pitch that is compatible with conventional printed wiring circuit board technology. If the intermediate substrate is substantially larger than the size of the semiconductor chip, then the advantage of small chip size is lost, as is the advantage of short electrical lead length that improves the ability to operate the circuit at very high operating frequencies. While this has been addressed by reducing the size of the intermediate substrate and employing next-level substrate technologies capable of finer line widths and smaller features, the rigidity of the intermediate substrate has again posed some difficulties.
The difficulties of rigid intermediate substrates have been addressed by making the substrates of specialized materials that are referred to as being xe2x80x9cflexible,xe2x80x9d such as very thin polyimide and other so-called xe2x80x9cflexiblexe2x80x9d conventional substrates on which printed wiring conductors and plated through holes can be formed by conventional methods. But, such substrate materials are not truly flexible in that they do not have a low modulus of elasticity, but only flex to a greater extent because they have been made of much thinner material having a high modulus of elasticity. Conventional materials, such as polyimide sheet, have a high modulus of elasticity, e.g., a modulus greater than 70,000 kg/cm2 (1,000,000 psi). In addition, the use of such materials and conventional fabrication methods results in an increased cost that is undesirable and may require assembly processes that are more difficult or expensive to perform.
Although certain intermediate substrates have been devised to avoid some of these difficulties, these substrates tend to be most beneficial when they are relatively thin. The thickness of the dielectric layer thereof and the length of the conductors passing through the dielectric layer is relatively short, e.g., on the order of the diameter thereof or less. If through conductors or vias having higher aspect ratios, i.e. higher ratios of their length to their diameter were available, then thicker intermediate substrates could be employed and could, for example, ease the buildup of undesirable thermal stress.
It would also be desirable if an interposer were to be suitable for a high-density (e.g., chip-scale) package, and yet avoid some of the technical disadvantage of conventional intermediate substrates. It would be further desirable if such interposer were to be attachable to the electronic device and next-level circuit substrate at a temperature that is much closer to room temperature, rather than at the much higher temperature needed to melt solder (e.g., 200-250xc2x0 C.) or to melt-flow high-temperature electrically-conductive thermoplastic adhesives (e.g., 100-150xc2x0 C.), to also ease the buildup of undesirable thermal stress. Such interposer might then be suitable for attachment to a semiconductor wafer separable into a plurality of electronic die and could be excised with the individual semiconductor die from the wafer.
Accordingly, there is a need for an intermediate circuit substrate or interposer that has higher aspect ratio via conductors and for a suitable method for making such interposer.
To this end, the method of the present invention comprises:
providing a sheet of metal;
removing part of the sheet of metal to leave a plurality of columnar conductors having distal ends projecting from a remaining web of the sheet of metal;
applying a layer of dielectric adhesive on the remaining web and surrounding the columnar conductors except for the distal ends thereof;
removing at least part of the remaining web to electrically isolate ones of the columnar conductors from others of the columnar conductors.
An electronic device according to the invention comprises an interposer having a layer of dielectric adhesive and a plurality of columnar conductors therethrough, wherein the columnar conductors include at least a section that is solid metal and have an aspect ratio of at least 1.5, an electronic component having contacts thereon, and connections of the contacts of the electronic component to respective first ends of ones of the columnar conductors of the interposer.